Aluminum-copper and related alloys were once the preferred alloys for forming interconnect structures in electronic devices such as integrated circuit chips. However, the present demands of the microelectronic industry for increased density and high performance (speed and efficiency) requires that the interconnect structures consist of pure or nearly pure copper. Performance is improved because the resistivity of copper and certain copper alloys is much lower than the resistivity of aluminum-copper. Also, narrow interconnect structures (lines) can be used, thus providing higher wiring densities.
Typically, copper interconnect structures are fabricated using a damascene processing method. In this process, trenches or vias are formed in a dielectric layer on a silicon wafer and then a metal liner (e.g. TaN/Ta) and a copper seed layer are deposited in the trenches/vias. The trenches/vias are further filled with copper. Chemical mechanical polishing (CMP) is then used to remove the copper overburden thereby providing a clean top copper surface coplanar with the dielectric layer. An etch stop or capping material such as SiNx, or a dielectric containing silicon, carbon and optionally nitrogen, is then deposited on the polished surfaces.
Many types of materials to cap copper have been proposed including both electroless and electrolytically plated metals as well as physical vapor deposited metal and organic-based capping materials. PVD or CVD capping materials are not selective and require a CMP or etching step to remove the film from the dielectric. Selective electroless deposition of some metal alloys, in particular of CoWP, has been shown to significantly improve electromigration lifetime, see Hu et al., “Reduced Electromigration of Cu Wires by Surface Coating.” Applied Physics Letters, 81(10), 2002, p. 1782. However, electroless processes typically require a seeding scheme (to start the nucleation of the deposit) as well as high plating temperatures, and are difficult to control especially for films less than 300 Å thick.
Electromigration and diffusion of copper through the capping material occurs primarily along the grain boundaries of the capping material. C.-K. Hu & al., “Electromigration in On-Chip Single/Dual Damascene Cu Interconnections”, J. Electrochem. Soc. 149, G408 (2002); C.-K. Hu & S. Reynolds, “CVD Cu Interconnections and Electromigration”, Electrochem. Soc. Procs. Vol. 97–25 (1997), p. 1514). As a result, it is desirable to optimize a capping material so as to minimize the grain boundary area and/or to lengthen the diffusion path along the existing grain boundaries. As explained by A. Kohn et al., in “Characterization of Electroless Deposited Co(W,P) Thin Films for Encapsulation of Copper Metallization”, Materials Science and Engineering A302 (2001) p. 18–25, the reasons for the observed difference in the diffusion barrier quality of PVD cobalt and electroless CoWP films is the result of the degree of crystallization and grain size in the two materials. “Single crystalline materials are expected to function as the best diffusion barriers because at low temperatures bulk diffusion is extremely small, and there are no grain boundaries for fast diffusion. However, deposition of single crystalline thin films can not yet be technologically realized. Consequently, the preferred microstructure of thin films for diffusion barrier applications is amorphous as it eliminates the fast diffusion paths along the grain boundaries.” Id., page 21.
Although amorphous materials are, in principle, very attractive for use as capping materials, many attempts by skilled researchers to obtain effective amorphous materials have failed. Attempts to optimize process conditions for existing amorphous materials have either provided materials that interdiffuse with copper too extensively to be of use (e.g., electroless NiP) or crystallize easily on heating, that is, at annealing temperatures of about 400° C. or greater. An optimal capping material will also have good adhesion to the copper conductor, and be a relatively thin, continuous film.
U.S. Pat. No. 5,695,810 describes the use of electroless deposited CoWP films as barrier layers including as a capping material for copper interconnect structures. One stated advantage of using an electroless deposited CoWP film for a barrier layer is that copper can be electrolessly deposited on CoWP without the need for an activation (seed) layer. The patent also appreciates that a slight amount of tungsten in the range of 2 to 7 atomic percent in the CoWP film can improve the barrier properties of the film over that of a cobalt phosphide film. The tungsten atoms preferentially become positioned at the grain boundaries. This observed effect is generally referred to as “stuffing” the grain boundaries of the CoP film.
However, as emphasized by Kohn, electroless deposited CoWP films are limited to about 8 to 10 atomic percent phosphorous. Also, electroless deposited films tend to be more crystalline than amorphous, and upon annealing the crystallinity of the film increases even further.
Rather than trying to improve upon the barrier properties of electroless deposited CoWP films, which by their nature are 1) limited to a maximum phosphorous content of 8 to 10 atomic percent, and 2) crystalline, Applicants sought a different approach to forming CoWP thin films in conjunction with adjacent copper conducting layers, in particular, copper interconnect structures.